The present invention relates to integrated circuit simulation technology, and more particularly to analysis of the timing of signal propagation.
Because of the long time required and the large expense involved for fabricating test versions of integrated circuits, it has become commonplace to simulate the operation of circuit designs as thoroughly as possible before fabricating a prototype. In this way corrections can be made before the time and expense of prototype fabrication is incurred. One parameter that is typically tested in these simulations is the propagation delay, from the output of a source node to the input of a destination node. Typically it is required that the propagation time must be short enough such that when added to the setup time requirement of the destination node, a signal asserted at the source node will reach the destination node soon enough to be stable when required by the destination node. The propagation time also must be long enough such that when added to the hold time requirement of the destination node, the release of a signal at the source node will not reach the destination node too early.
Process variations in semiconductor manufacturing have become critical factors to consider for circuit designs, especially as the device feature size shrinks into nanometer scale. Product yield is at increasing risk unless process variations and their impacts are properly modeled in the simulations. One area of process variations concerns metal interconnects. It has been found that the metal wire cross-section (height and width), as well as the spacing between adjacent metal lines, may vary by more than 10% from location to location on a single wafer and from wafer to wafer, leading to more than 20% fluctuation in resistance (R) and capacitance (C) relative to their nominal values. The values of R and C for an interconnect largely determine the signal propagation time from a source node to a destination node, so the uncertainty in R and C results in uncertainty in the propagation time. A product therefore may fail in timing if the large uncertainty in R and C is not properly taken into account when calculating propagation delays.
The uncertainties in resistance and capacitance can be taken into account during simulations by ensuring that the maximum propagation time in a particular interconnect is short enough such that when added to the setup time requirement of the destination node, a signal asserted at the source node will reach the destination node soon enough to be stable when required by the destination node; and that the minimum propagation time in the interconnect is long enough such that the release of a signal at the source node will not reach the destination node before the hold time requirement of the destination node expires. Thus it becomes important to know the minimum and maximum possible propagation times for each interconnect under study. One cannot determine these absolutely, of course, because there will always be a small possibility of particular set of conditions in which signals propagate slightly faster or slightly more slowly. Usually some practical definition of “minimum” and “maximum” is adopted.
One common method for determining the minimum and maximum propagation times for an interconnect is to assume that the whole design is either under the “best case” or “worst case” for capacitance (C), or for the product of resistance and capacitance (RC). This practice may give rise to misleading results for two reasons. First, R and C variations are often correlated: a particular interconnect that turns out on fabrication to exhibit better capacitance performance, also tends to exhibit worse resistance performance, and vice-versa. Second, the circuit responses to variations in R or C often depend on the driving strength of the source and the R and C values themselves.
For instance, propagation delays are sometimes assumed to be shortest when the C value is the smallest. But a variation in which C is smallest is often the same variation that exhibits the largest value for R, which typically would be assumed to yield the longest propagation delay. One therefore cannot generalize that a device in which a particular interconnect has a capacitance at the small end of the range of possible capacitances, or a resistance*capacitance product at the small end of the range of possible such products, yields the shortest propagation delays. Nor can one generalize that a device in which a particular interconnect has a capacitance at the large end of the range of possible capacitances, or a resistance*capacitance product at the high end of the range of possible products, yields the longest propagation delay for the particular interconnect. Furthermore, it can be seen that if the entire design is analyzed using “best case” capacitances, conditions may be such that one individual interconnect may exhibit the shortest propagation delay while another individual interconnect may exhibit the longest propagation delay. If the two interconnects happen to be in the same delay path (e.g. in a chain of several drivers interconnected by metal wires), one would not be able to assert whether the overall path delay is the shortest or longest. Consequently, one does not know whether the delay path satisfies the timing requirements for the design to meet product specifications.
Therefore, there is a need to assess the effects on interconnect signal propagation delay caused by different process variations, more accurately than is possible using existing methods.